1. Technical Field
The present disclosure relates to a pad having a test logic circuit for a chain test and, more particularly, to a pad unit having a test logic circuit for preventing noise propagation through a test chain and a method of driving a system including the pad.
2. Discussion of Related Art
A logic test is typically performed to check a characteristic of input/output pads. Using such a logic test may reduce the time and cost of separately testing the pins of a semiconductor device. A logic chain may be used for the logic test. In the logic test input/output pads, High Level Input Voltage (VIH), Low Level Input Voltage (VIL), and Input Signal Fault Detection may be considered.
FIGS. 1A and 1B are diagrams illustrating conventional input pads.
Referring to FIG. 1, an input pad 110 does not include a logic circuit. Thus, a chain test is performed after connecting an external logic chain (not shown) between the input pad 110 and an output pad (not shown) at Y in a logic test mode.
The input pad 110 is used only for a normal operation mode of receiving an input signal, and cannot provide a test function. A designer of a semiconductor device may connect an external test logic circuit, such as at Y, to the input pad 110 as a logic chain to test a signal characteristic of the input pad 110.
Referring to FIG. 1B, a test logic circuit having a NAND gate 130 is coupled to an input pad 120. In this situation, the designer of the semiconductor device does not need the external test logic circuit when using the pad 120 having the test logic circuit as shown in FIG. 1B.
The test logic circuit having the NAND gate 130 may form a logic chain with test logic circuits of other pads connected at Y. The NAND gate 130 included in the test logic circuit shown in FIG. 1B may be referred to as a NAND Primitive for a NAND gate logic chain and has a second input SI from a preceding stage and an output SO.
FIG. 2 is a diagram illustrating a configuration for performing a chain test using the test logic circuit shown in FIG. 1B.
Input stages 210, 220, and 230 may be implemented with input pads 211, 221, and 231, and may further include additional termination resistors that are shown for impedance matching, as well as the buffers that are shown.
Input signals IN_D1, IN_D2, and IN_D3 that are provided through input pads 211, 221, and 231 are ultimately transmitted to an internal circuit (not shown), such as an internal core logic circuit of the system, in a normal operation mode. The input signals IN_D1, IN_D2, and IN_D3 are transmitted to a logic chain 240 in a scan test mode. The input signals IN_D1, IN_D2, and IN_D3 may be provided from an external test device (not shown) in the scan test mode.
Test logic circuits 241, 242, and 243 are respectively coupled to the input pads 211, 221, and 231, and form the logic chain 240, as shown in FIG. 2.
An output unit 250 receives test data from the logic chain 240. The output unit 250 provides a test result OUT_D through a test output pad 251 in response to an output test enable signal OUT_EN.
The chain test using the logic chain 240 is performed as follows.
A first test signal IN_D1 input via an input pad 211 and a chain input signal SI1 from a preceding test logic circuit (not shown) are provided to a first test logic circuit 241. An output signal SO1 of the first test logic circuit 241 is provided to a second test logic circuit 242 as a chain input signal SI2.
A second test signal IN_D2 input via an input pad 221 and the chain input signal SI2 are provided to the second test logic circuit 242. An output signal SO2 of the second test logic circuit 242 is provided to the third test logic circuit 243 as a chain input signal SI3.
A third test signal IN_D3 input via an input pad 231 and the chain input signal SI3 are provided to the third test logic circuit 243. An output signal SO3 of the third test logic circuit 243 is outputted to a test device (not shown) through an output pad 251 of the output unit 250 in response to an output test enable signal OUT_EN. The test device (not shown) checks whether the output signal OUT_D of the output unit 250 corresponds to an expected value, and determines whether the chain test is successful.
The normal operation may be performed after the chain test is determined to be successful, and the input signals IN_D1, IN_D2, and IN_D3 provided through the input pads 211, 221, and 231 may be transmitted to the internal core logic circuit (not shown).
The logic chain 240 can adversely influence the input signal in the normal operation mode because a noise component in the input signals may propagate through the logic chain 240.
For example, when a clock signal having a bandwidth of 1 Mhz to 100 Mhz is provided to a phase-locked-loop circuit, an initially generated low-level noise may be amplified due to a generation of signals having the same phases, and the amplified noise may cause a malfunction. This influence of noise may be ignored in the case that the power-supply voltage is a very high level. Many recent semiconductor devices, however, need to operate at a low power-supply voltage to achieve low cost, high speed and low power consumption. The adverse influence of the noise becomes more serious as the power-supply voltage is lowered.